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* [ARM64_DYNAREC] Added 66 0F 3A 40 opcode (with tests)ptitSeb2023-11-061-0/+5
* [TESTS] Disable compiler optimizations for test17 and some related fixes (#677)Yang Liu2023-04-091-18/+19
* Improved test17 and finetuned factorio profile to disable FASTROUND on DynarecptitSeb2023-04-011-2/+13
* More work on test17, and handling -NAN on divsdptitSeb2022-04-011-1/+9
* Added more sse2 opcode to test17, and added nan handling to SQRTSD and MULSD ...ptitSeb2022-04-011-7/+128
* Even more test17 coverageptitSeb2022-04-011-2/+51
* More coverage for test17, and added NaN handling to 66 0F 7C opcodeptitSeb2022-04-011-1/+54
* More test17 coverageptitSeb2022-03-311-0/+6
* More cases to test17, and added -NAN generation to divpd ([DYNAREC] too)ptitSeb2022-03-311-0/+4
* More test17 impovements, fixed NAN for mulpd ([DYNAREC] too, introducing BOX6...ptitSeb2022-03-311-0/+19
* Improved test17 (sse), and fixed NAN bordercase for PSQRTPD opcodeptitSeb2022-03-311-3/+58
* Improved test17 ([DYNAREC] Added 66 0F 38 16 opcode, fixed 66 0F 38 24/34 opc...ptitSeb2022-03-301-10/+46
* Improved and enhanced test17 (SSE testing)ptitSeb2022-03-301-81/+124
* Improved CMPSS/CMPSD opcodes, improved test17 ([DYNAREC] too, and improved MI...ptitSeb2021-11-071-27/+177
* [DYNAREC] Fixed DIV opcode, and added test17 about div/idivptitSeb2021-07-021-0/+50