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authorChristian Krinitsin <mail@krinitsin.com>2025-05-21 21:21:26 +0200
committerChristian Krinitsin <mail@krinitsin.com>2025-05-21 21:21:26 +0200
commit4b927bc37359dec23f67d3427fc982945f24f404 (patch)
tree245449ef9146942dc7fffd0235b48b7e70a00bf2 /gitlab/issues/target_missing/host_missing/accel_missing/2350.toml
parentaa8bd79cec7bf6790ddb01d156c2ef2201abbaab (diff)
downloademulator-bug-study-4b927bc37359dec23f67d3427fc982945f24f404.tar.gz
emulator-bug-study-4b927bc37359dec23f67d3427fc982945f24f404.zip
add gitlab issues in toml format
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+id = 2350
+title = "Incorrect RNG_CTRL and RNG_DATA_OUTPUT register offets for Aspeed AST2600 A3"
+state = "opened"
+created_at = "2024-05-17T14:10:08.390Z"
+closed_at = "n/a"
+labels = []
+url = "https://gitlab.com/qemu-project/qemu/-/issues/2350"
+host-os = "- OS/kernel version:"
+host-arch = "- QEMU flavor:"
+qemu-version = "- QEMU command line:"
+guest-os = "- OS/kernel version:"
+guest-arch = "## Description of problem"
+description = """hw/misc/aspeed_scu.c has the following lines:
+
+#define AST2600_RNG_CTRL          TO_REG(0x524)
+#define AST2600_RNG_DATA          TO_REG(0x540)
+
+The Datasheet for the AST2600 A3 lists the offsets as 0x520 for RNG_CTRL and 0x524 for RNG_DATA.  I can confirm that these addresses are correct on the hardware.  I don't know if the offsets changed from a previous revision, but since qemu fills the SILICON_REV register with the AST2600_A3_SILICON_REV value for the AST2600, it makes sense to me that it would use the A3 register offsets."""
+reproduce = """1.
+2.
+3."""
+additional = """"""