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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 14:51:13 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-05-30 14:51:13 +0000 |
| commit | 225caa38269323af1bfc2daadff5ec8bd930747f (patch) | |
| tree | e0a5fefde9ee100ba6f32fb36de6707490e4164e /mailinglist/output_launchpad/1863247 | |
| parent | 904141bfb8d5385b75eb3b7afec1dcda89af65a7 (diff) | |
| download | emulator-bug-study-225caa38269323af1bfc2daadff5ec8bd930747f.tar.gz emulator-bug-study-225caa38269323af1bfc2daadff5ec8bd930747f.zip | |
add mailinglist scraper results
Diffstat (limited to 'mailinglist/output_launchpad/1863247')
| -rw-r--r-- | mailinglist/output_launchpad/1863247 | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/mailinglist/output_launchpad/1863247 b/mailinglist/output_launchpad/1863247 new file mode 100644 index 00000000..4e690f69 --- /dev/null +++ b/mailinglist/output_launchpad/1863247 @@ -0,0 +1,20 @@ +AArch64 EXT instruction for V register does not clear MSB side bits + +On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu-aarch64 seems to hold the value. + +Example +ext v0.16b, v1.16b v2.16b, 8 + +After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width. + +Yep. + +Fixed here: +https://git.qemu.org/?p=qemu.git;a=commitdiff;h=78cedfabd53b + + +Thank you for bug fix. +I found trn1, trn2, zip1, zip2, uz1, uz2 instructions seem to have same bug. + +All of those, and tbl, tbx, ins, are fixed in the three subsequent commits. + |