add new classifier result

1 files changed, 48 insertions, 0 deletions

diff --git a/results/classifier/105/device/1793 b/results/classifier/105/device/1793
new file mode 100644
index 00000000..0fef2cef
--- /dev/null
+++ b/results/classifier/105/device/1793
@@ -0,0 +1,48 @@
+device: 0.886
+instruction: 0.857
+graphic: 0.846
+other: 0.744
+vnc: 0.719
+boot: 0.705
+semantic: 0.671
+network: 0.668
+assembly: 0.614
+mistranslation: 0.599
+socket: 0.565
+KVM: 0.255
+
+getauxval(AT_HWCAP) returns different value under qemu-system-riscv64 and qemu-riscv64
+Description of problem:
+I have a test program that checks for the presence of the RISC-V Vector extension (RVV) via getauxval().
+
+```c
+#include <sys/auxv.h>
+#include <stdio.h>
+
+#define ISA_V_HWCAP (1 << ('v' - 'a'))
+
+void main() {
+  unsigned long hw_cap = getauxval(AT_HWCAP);
+  printf("RVV %s\n", hw_cap & ISA_V_HWCAP ? "detected" : "not found");
+}
+```
+
+When run inside `qemu-system-riscv64` with a 6.5-rc3 kernel where `CONFIG_RISCV_ISA_V=y` and `CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y` it correctly shows:
+
+```
+$ ./hwcap
+RVV detected
+```
+
+However when executed with `qemu-riscv64` it does not return the V bit set:
+
+```
+$ qemu-riscv64 hwcap
+RVV not found
+```
+Steps to reproduce:
+1. Boot 6.5-rc3 kernel with `CONFIG_RISCV_ISA_V=y` and `CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y`
+2. In guest run test program hwcap (source above)
+3. On host run `qemu-riscv64 hwcap`
+Additional information:
+