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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-06-03 12:04:13 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-06-03 12:04:13 +0000 |
| commit | 256709d2eb3fd80d768a99964be5caa61effa2a0 (patch) | |
| tree | 05b2352fba70923126836a64b6a0de43902e976a /results/classifier/105/device/2350 | |
| parent | 2ab14fa96a6c5484b5e4ba8337551bb8dcc79cc5 (diff) | |
| download | emulator-bug-study-256709d2eb3fd80d768a99964be5caa61effa2a0.tar.gz emulator-bug-study-256709d2eb3fd80d768a99964be5caa61effa2a0.zip | |
add new classifier result
Diffstat (limited to 'results/classifier/105/device/2350')
| -rw-r--r-- | results/classifier/105/device/2350 | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/results/classifier/105/device/2350 b/results/classifier/105/device/2350 new file mode 100644 index 00000000..f3f085c9 --- /dev/null +++ b/results/classifier/105/device/2350 @@ -0,0 +1,27 @@ +device: 0.872 +graphic: 0.721 +instruction: 0.686 +vnc: 0.666 +mistranslation: 0.649 +network: 0.614 +socket: 0.464 +semantic: 0.354 +boot: 0.187 +assembly: 0.165 +KVM: 0.115 +other: 0.111 + +Incorrect RNG_CTRL and RNG_DATA_OUTPUT register offets for Aspeed AST2600 A3 +Description of problem: +hw/misc/aspeed_scu.c has the following lines: + +#define AST2600_RNG_CTRL TO_REG(0x524) +#define AST2600_RNG_DATA TO_REG(0x540) + +The Datasheet for the AST2600 A3 lists the offsets as 0x520 for RNG_CTRL and 0x524 for RNG_DATA. I can confirm that these addresses are correct on the hardware. I don't know if the offsets changed from a previous revision, but since qemu fills the SILICON_REV register with the AST2600_A3_SILICON_REV value for the AST2600, it makes sense to me that it would use the A3 register offsets. +Steps to reproduce: +1. +2. +3. +Additional information: + |