add new classifier result

1 files changed, 37 insertions, 0 deletions

diff --git a/results/classifier/105/instruction/1463338 b/results/classifier/105/instruction/1463338
new file mode 100644
index 00000000..4a46291d
--- /dev/null
+++ b/results/classifier/105/instruction/1463338
@@ -0,0 +1,37 @@
+instruction: 0.726
+mistranslation: 0.709
+device: 0.586
+other: 0.564
+graphic: 0.534
+network: 0.454
+semantic: 0.432
+socket: 0.386
+assembly: 0.284
+vnc: 0.280
+boot: 0.258
+KVM: 0.153
+
+qemu-system-arm injects #UND exception with wrong PC
+
+Usually all accesses to coprocessor registers are only possible in PL1 or higher. When accessing a coprocessor register in user mode, QEMU generates a trap and the PC of the trapping instruction is passed to the OS with an offset of+ 4. Some coprocessor registers can be configured to allow access to them in usermode (PL0). The latest qemu-git (ee09f84e6bf5383a23c9624115c26b72aa1e076c) seems to add an offest of 8 instead of four if such a register is accessed from user mode. This happens only if the coprocessors register that is accessed might also be accessed from PL0. In case all accesses to the coprocessor register from PL0 cause a trap, qemu injects the #UND trap with the correct PC value. 
+
+Attached is a small test program that installs a signal handler for "SIGILL". On a pandaboard the progam prints "Val=0x2 Val2=0x2" whereas on the latest "qemu-system-arm" the output is : "Val=0x1 Val2=0x2"
+
+Qemu was configured with: "./configure --python=`which python2.7` --target-list=arm-softmmu"
+The test can be compiled with: "gcc -g -static test2.c -o test2"
+
+If further information is needed, feel free to ask.
+
+Regards,
+
+Robert
+
+
+
+Thanks for the clear bug report and the test case. I've submitted a patch which fixes this:
+http://patchwork.ozlabs.org/patch/482273/
+
+
+Should be in 2.6.
+
+