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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 16:27:09 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 16:27:09 +0000 |
| commit | 4d9e26c0333abd39bdbd039dcdb30ed429c475ba (patch) | |
| tree | 4010d5fb3e8bc48c110a2c1ff2a16b8648cb86bb /results/classifier/accel-gemma3:12b/kvm/1832535 | |
| parent | 5541099586dbd6018574cb44e1934907c121526f (diff) | |
| download | emulator-bug-study-4d9e26c0333abd39bdbd039dcdb30ed429c475ba.tar.gz emulator-bug-study-4d9e26c0333abd39bdbd039dcdb30ed429c475ba.zip | |
add gemma accelerator classification results
Diffstat (limited to 'results/classifier/accel-gemma3:12b/kvm/1832535')
| -rw-r--r-- | results/classifier/accel-gemma3:12b/kvm/1832535 | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/results/classifier/accel-gemma3:12b/kvm/1832535 b/results/classifier/accel-gemma3:12b/kvm/1832535 new file mode 100644 index 00000000..1d904065 --- /dev/null +++ b/results/classifier/accel-gemma3:12b/kvm/1832535 @@ -0,0 +1,13 @@ + +[riscv/regression] Missing tlb flush introduced in refactoring + +Hello, + +In qemu-system-riscv64, following a QEMU update, I get all sort of weird and not easily reproducible crashes in my risc-v guest. + +I have bissected this issue to commit c7b951718815694284501ed01fec7acb8654db7b. +Some TLB flushes were removed in the following places: +target/riscv/cpu_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice) +target/riscv/op_helper.c: `csr_write_helper(env, s, CSR_MSTATUS);` -> `env->mstatus = s;` (twice) + +Adding TLB flushes in all 4 places fixes the issues for me.
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