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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
| commit | d0c85e36e4de67af628d54e9ab577cc3fad7796a (patch) | |
| tree | f8f784b0f04343b90516a338d6df81df3a85dfa2 /results/classifier/deepseek-2-tmp/output/hypervisor/1863685 | |
| parent | 7f4364274750eb8cb39a3e7493132fca1c01232e (diff) | |
| download | emulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.tar.gz emulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.zip | |
add deepseek and gemma results
Diffstat (limited to 'results/classifier/deepseek-2-tmp/output/hypervisor/1863685')
| -rw-r--r-- | results/classifier/deepseek-2-tmp/output/hypervisor/1863685 | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/results/classifier/deepseek-2-tmp/output/hypervisor/1863685 b/results/classifier/deepseek-2-tmp/output/hypervisor/1863685 deleted file mode 100644 index b399ca7d..00000000 --- a/results/classifier/deepseek-2-tmp/output/hypervisor/1863685 +++ /dev/null @@ -1,9 +0,0 @@ - -ARM: HCR.TSW traps are not implemented - -On 32-bit and 64-bit ARM platforms, setting HCR.TSW is supposed to "Trap data or unified cache maintenance instructions that operate by Set/Way." Quoting the ARM manual: - -If EL1 is using AArch64 state, accesses to DC ISW, DC CSW, DC CISW are trapped to EL2, reported using EC syndrome value 0x18. -If EL1 is using AArch32 state, accesses to DCISW, DCCSW, DCCISW are trapped to EL2, reported using EC syndrome value 0x03. - -However, QEMU does not trap those instructions/registers. This was tested on the branch master of the git repo. \ No newline at end of file |