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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
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| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
| commit | d0c85e36e4de67af628d54e9ab577cc3fad7796a (patch) | |
| tree | f8f784b0f04343b90516a338d6df81df3a85dfa2 /results/classifier/gemma3:12b/device/2350 | |
| parent | 7f4364274750eb8cb39a3e7493132fca1c01232e (diff) | |
| download | emulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.tar.gz emulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.zip | |
add deepseek and gemma results
Diffstat (limited to 'results/classifier/gemma3:12b/device/2350')
| -rw-r--r-- | results/classifier/gemma3:12b/device/2350 | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/device/2350 b/results/classifier/gemma3:12b/device/2350 new file mode 100644 index 00000000..a5d625d4 --- /dev/null +++ b/results/classifier/gemma3:12b/device/2350 @@ -0,0 +1,15 @@ + +Incorrect RNG_CTRL and RNG_DATA_OUTPUT register offets for Aspeed AST2600 A3 +Description of problem: +hw/misc/aspeed_scu.c has the following lines: + +#define AST2600_RNG_CTRL TO_REG(0x524) +#define AST2600_RNG_DATA TO_REG(0x540) + +The Datasheet for the AST2600 A3 lists the offsets as 0x520 for RNG_CTRL and 0x524 for RNG_DATA. I can confirm that these addresses are correct on the hardware. I don't know if the offsets changed from a previous revision, but since qemu fills the SILICON_REV register with the AST2600_A3_SILICON_REV value for the AST2600, it makes sense to me that it would use the A3 register offsets. +Steps to reproduce: +1. +2. +3. +Additional information: + |