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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
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| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-03 07:27:52 +0000 |
| commit | d0c85e36e4de67af628d54e9ab577cc3fad7796a (patch) | |
| tree | f8f784b0f04343b90516a338d6df81df3a85dfa2 /results/classifier/gemma3:12b/hypervisor/1793 | |
| parent | 7f4364274750eb8cb39a3e7493132fca1c01232e (diff) | |
| download | emulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.tar.gz emulator-bug-study-d0c85e36e4de67af628d54e9ab577cc3fad7796a.zip | |
add deepseek and gemma results
Diffstat (limited to 'results/classifier/gemma3:12b/hypervisor/1793')
| -rw-r--r-- | results/classifier/gemma3:12b/hypervisor/1793 | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/hypervisor/1793 b/results/classifier/gemma3:12b/hypervisor/1793 new file mode 100644 index 00000000..2fa82821 --- /dev/null +++ b/results/classifier/gemma3:12b/hypervisor/1793 @@ -0,0 +1,36 @@ + +getauxval(AT_HWCAP) returns different value under qemu-system-riscv64 and qemu-riscv64 +Description of problem: +I have a test program that checks for the presence of the RISC-V Vector extension (RVV) via getauxval(). + +```c +#include <sys/auxv.h> +#include <stdio.h> + +#define ISA_V_HWCAP (1 << ('v' - 'a')) + +void main() { + unsigned long hw_cap = getauxval(AT_HWCAP); + printf("RVV %s\n", hw_cap & ISA_V_HWCAP ? "detected" : "not found"); +} +``` + +When run inside `qemu-system-riscv64` with a 6.5-rc3 kernel where `CONFIG_RISCV_ISA_V=y` and `CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y` it correctly shows: + +``` +$ ./hwcap +RVV detected +``` + +However when executed with `qemu-riscv64` it does not return the V bit set: + +``` +$ qemu-riscv64 hwcap +RVV not found +``` +Steps to reproduce: +1. Boot 6.5-rc3 kernel with `CONFIG_RISCV_ISA_V=y` and `CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y` +2. In guest run test program hwcap (source above) +3. On host run `qemu-riscv64 hwcap` +Additional information: + |