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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-07 17:18:14 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-07 17:18:14 +0000 |
| commit | 61361f925d4914a6608a0076e64cc2399311ed5f (patch) | |
| tree | 6f717c2ff0b11d7493e60da9757818d119cfb541 /results/classifier/phi4:14b/output/instruction/1079080 | |
| parent | 238ec2b7cc1557d6f34c33cc482e4d0cd3e266dd (diff) | |
| download | emulator-bug-study-61361f925d4914a6608a0076e64cc2399311ed5f.tar.gz emulator-bug-study-61361f925d4914a6608a0076e64cc2399311ed5f.zip | |
add new results
Diffstat (limited to 'results/classifier/phi4:14b/output/instruction/1079080')
| -rw-r--r-- | results/classifier/phi4:14b/output/instruction/1079080 | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/results/classifier/phi4:14b/output/instruction/1079080 b/results/classifier/phi4:14b/output/instruction/1079080 new file mode 100644 index 00000000..069bd5e2 --- /dev/null +++ b/results/classifier/phi4:14b/output/instruction/1079080 @@ -0,0 +1,13 @@ + + +ARM instruction "srs" wrong behaviour + +Quote from ARM Architecture Reference Manual ARMv7-A and ARMv7-R : +"Store Return State stores the LR and SPSR of the current mode to the stack of a specified mode" + +Problem: +When executing this instruction, the register stored is CPSR instead of SPSR. + +Context: +Using QEMU 1.2.0 to simulate a Zynq application (processor Cortex-a9 mpcore) with the following command line: +qemu-system-arm -M xilinx-zynq-a9 -m 512 -serial null -serial mon:stdio -dtb /home/vcesson/workspace/xilinx_zynq.dtb -kernel install/tests/io/serial/current/tests/serial2 -S -s -nographic \ No newline at end of file |