restructure results

1 files changed, 0 insertions, 29 deletions

diff --git a/results/classifier/semantic-bugs/assembly/904 b/results/classifier/semantic-bugs/assembly/904
deleted file mode 100644
index 4946b814..00000000
--- a/results/classifier/semantic-bugs/assembly/904
+++ /dev/null
@@ -1,29 +0,0 @@
-assembly: 0.991
-instruction: 0.939
-graphic: 0.875
-device: 0.846
-semantic: 0.662
-network: 0.599
-mistranslation: 0.507
-vnc: 0.485
-boot: 0.425
-socket: 0.381
-KVM: 0.219
-other: 0.191
-
-RISC-V: Cannot set SEIP bit of mip csr register in M mode
-Description of problem:
-
-Steps to reproduce:
-1.   run assembly instructions **in M mode**: 
-```
-not t0, x0    // set t0 to 0b11..11
-csrs mip, t0  // write mip with t0, mip registers are WARL(Write Any Values, Reads Legal Values)
-csrr t1, mip  // read value from mip to t1
-```
-2.   GDB enters the command `display/z $t1` to see that the content of the t1 register is 0x466, which means that the SEIP bit of mip is not set.
-3.   According to page 47 of [riscv-privileged-20211203](https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf), `SEIP is writable in mip`.
-4.   According to page 81 of the same manual,`If implemented, SEIP is read-only in sip`.
-5.   However, the above code and results show that the SEIP bit of mip cannot be set by software **in M mode**.
-Additional information:
-