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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-08 13:28:15 +0200 |
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| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-08 13:28:28 +0200 |
| commit | 5aa276efcbd67f4300ca1a7f809c6e00aadb03da (patch) | |
| tree | 9b8f0e074014cda8d42f5a97a95bc25082d8b764 /results/classifier/zero-shot-user-mode/instruction/1079080 | |
| parent | 1a3c4faf4e0a25ed0b86e8739d5319a634cb9112 (diff) | |
| download | emulator-bug-study-5aa276efcbd67f4300ca1a7f809c6e00aadb03da.tar.gz emulator-bug-study-5aa276efcbd67f4300ca1a7f809c6e00aadb03da.zip | |
restructure results
Diffstat (limited to 'results/classifier/zero-shot-user-mode/instruction/1079080')
| -rw-r--r-- | results/classifier/zero-shot-user-mode/instruction/1079080 | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/results/classifier/zero-shot-user-mode/instruction/1079080 b/results/classifier/zero-shot-user-mode/instruction/1079080 new file mode 100644 index 00000000..486afa7a --- /dev/null +++ b/results/classifier/zero-shot-user-mode/instruction/1079080 @@ -0,0 +1,16 @@ +instruction: 0.848 +runtime: 0.112 +syscall: 0.040 + + +ARM instruction "srs" wrong behaviour + +Quote from ARM Architecture Reference Manual ARMv7-A and ARMv7-R : +"Store Return State stores the LR and SPSR of the current mode to the stack of a specified mode" + +Problem: +When executing this instruction, the register stored is CPSR instead of SPSR. + +Context: +Using QEMU 1.2.0 to simulate a Zynq application (processor Cortex-a9 mpcore) with the following command line: +qemu-system-arm -M xilinx-zynq-a9 -m 512 -serial null -serial mon:stdio -dtb /home/vcesson/workspace/xilinx_zynq.dtb -kernel install/tests/io/serial/current/tests/serial2 -S -s -nographic \ No newline at end of file |