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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-07 17:23:11 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-07 17:23:11 +0000 |
| commit | c50b0c4da17b6e83640e4ed2380fffb5f507c846 (patch) | |
| tree | b4f203fce1380e2ea3578a784bb8ee060fe42cbd /results/classifier/zero-shot-user-mode/output/instruction/1862167 | |
| parent | 61361f925d4914a6608a0076e64cc2399311ed5f (diff) | |
| download | emulator-bug-study-c50b0c4da17b6e83640e4ed2380fffb5f507c846.tar.gz emulator-bug-study-c50b0c4da17b6e83640e4ed2380fffb5f507c846.zip | |
add zero-shot results
Diffstat (limited to 'results/classifier/zero-shot-user-mode/output/instruction/1862167')
| -rw-r--r-- | results/classifier/zero-shot-user-mode/output/instruction/1862167 | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/results/classifier/zero-shot-user-mode/output/instruction/1862167 b/results/classifier/zero-shot-user-mode/output/instruction/1862167 new file mode 100644 index 00000000..a713f071 --- /dev/null +++ b/results/classifier/zero-shot-user-mode/output/instruction/1862167 @@ -0,0 +1,9 @@ +instruction: 0.742 +runtime: 0.150 +syscall: 0.107 + + + +Variation of SVE register size (qemu-user-aarch64) + +Specification of ARMv8-A SVE extention allows various values for the size of the SVE register. On the other hand, it seems that the current qemu-aarch64 supports only the maximum length of 2048 bits as the SVE register size. I am writing an assembler program for a CPU that is compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when this is run with qemu-user-aarch64, a 2048-bit load / store instruction is executed This causes a segmentation fault. Shouldn't qeum-user-aarch64 have an option to specify the SVE register size? \ No newline at end of file |