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| author | Christian Krinitsin <mail@krinitsin.com> | 2025-07-07 17:23:11 +0000 |
|---|---|---|
| committer | Christian Krinitsin <mail@krinitsin.com> | 2025-07-07 17:23:11 +0000 |
| commit | c50b0c4da17b6e83640e4ed2380fffb5f507c846 (patch) | |
| tree | b4f203fce1380e2ea3578a784bb8ee060fe42cbd /results/classifier/zero-shot-user-mode/output/instruction/1863247 | |
| parent | 61361f925d4914a6608a0076e64cc2399311ed5f (diff) | |
| download | emulator-bug-study-c50b0c4da17b6e83640e4ed2380fffb5f507c846.tar.gz emulator-bug-study-c50b0c4da17b6e83640e4ed2380fffb5f507c846.zip | |
add zero-shot results
Diffstat (limited to 'results/classifier/zero-shot-user-mode/output/instruction/1863247')
| -rw-r--r-- | results/classifier/zero-shot-user-mode/output/instruction/1863247 | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/results/classifier/zero-shot-user-mode/output/instruction/1863247 b/results/classifier/zero-shot-user-mode/output/instruction/1863247 new file mode 100644 index 00000000..383a023c --- /dev/null +++ b/results/classifier/zero-shot-user-mode/output/instruction/1863247 @@ -0,0 +1,14 @@ +instruction: 0.878 +runtime: 0.078 +syscall: 0.044 + + + +AArch64 EXT instruction for V register does not clear MSB side bits + +On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu-aarch64 seems to hold the value. + +Example +ext v0.16b, v1.16b v2.16b, 8 + +After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width. \ No newline at end of file |