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diff --git a/gitlab/issues/target_arm/host_missing/accel_TCG/1062.toml b/gitlab/issues/target_arm/host_missing/accel_TCG/1062.toml
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+id = 1062
+title = "AArch64: SCR_EL3.RW behaves incorrectly for CPUs with no AArch32"
+state = "closed"
+created_at = "2022-06-05T04:51:08.258Z"
+closed_at = "2022-06-10T23:03:46.969Z"
+labels = ["Closed::Fixed", "accel: TCG", "target: arm"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1062"
+host-os = "Any"
+host-arch = "Any"
+qemu-version = "QEMU emulator version 7.0.0 (v6.2.0-3146-g7e0e865ad5-dirty)"
+guest-os = "n/a"
+guest-arch = "ARM"
+description = """In the ARM DDI 0487G.a, D13-3572, the SCR_EL3.RW bit is defined as RAO/WI if both EL2 and EL1 don't support Aarch32. However, the function `scr_write` in `target/arm/helper.c` does not reflect this behavior, even though it checks for Aarch32 EL1 support.
+
+This would break this EL3 code, which should run on cpu reset to attempt to return to EL1:
+```asm
+mov x1, #((1<<0)|(1<<2)|(1<<6)|(1<<7)|(1<<8)|(1<<9)) ; EL1h, DAIF masked
+mov SPSR_EL3, x1
+adr x1, 1f
+msr ELR_EL3, x1
+eret
+1:
+; something something
+```"""
+reproduce = "n/a"
+additional = """"""