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diff --git a/gitlab/issues/target_arm/host_missing/accel_TCG/2419.toml b/gitlab/issues/target_arm/host_missing/accel_TCG/2419.toml
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+id = 2419
+title = "ldapr_stlr_i instructions doesn't consider signed offset"
+state = "closed"
+created_at = "2024-07-02T13:05:24.359Z"
+closed_at = "2024-07-19T01:20:04.204Z"
+labels = ["accel: TCG", "kind::Bug", "target: arm", "workflow::Patch available"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/2419"
+host-os = "Linux"
+host-arch = "ARM"
+qemu-version = "8.1.3"
+guest-os = "Linux"
+guest-arch = "ARM"
+description = """The format ldapr_stlr_i models the load acquire / store release immediate instructions. \\
+These instructions has a bug in the sign extension calculation of the imm field. \\
+imm should be defined as s9 instead of 9.
+
+@ldapr_stlr_i   .. ...... .. . imm:9 .. rn:5 rt:5 &ldapr_stlr_i
+
+Should be changed to:
+
+@ldapr_stlr_i   .. ...... .. . imm:s9 .. rn:5 rt:5 &ldapr_stlr_i"""
+reproduce = """1. Run ARM target
+2. Generate any ldapr_stlr_i instructions (for example: LDAPUR)
+3. When the imm value is negative, the immediate calculation is done wrong. In case the calculation leads to an undefined location, QEMU will fail."""
+additional = """In trans_LDAPR_i (translate-a64.c), when imm field is negative, the value of a->imm will be 512-x instead of x. \\
+I already fixed the issue by adding the s9 to the imm field. This made a call to sextend32 for imm instead of extend32 in the generated file build/libqemu-aarch64-softmmu.fa.p/decode-a64.c.inc"""