1 files changed, 0 insertions, 42 deletions

diff --git a/gitlab/issues/target_riscv/host_missing/accel_TCG/1028.toml b/gitlab/issues/target_riscv/host_missing/accel_TCG/1028.toml
deleted file mode 100644
index c3cb8fd6..00000000
--- a/gitlab/issues/target_riscv/host_missing/accel_TCG/1028.toml
+++ /dev/null
@@ -1,42 +0,0 @@
-id = 1028
-title = "Assert fail for RISC-V RVV vmv.v.x for e64, vl == vl_max on RV32 guest"
-state = "closed"
-created_at = "2022-05-17T10:13:33.837Z"
-closed_at = "2022-06-09T01:27:05.150Z"
-labels = ["accel: TCG", "target: riscv"]
-url = "https://gitlab.com/qemu-project/qemu/-/issues/1028"
-host-os = "(CentOS-8.5.2111)"
-host-arch = "(x86)"
-qemu-version = "(7.0.0)"
-guest-os = "(baremetal)"
-guest-arch = "(RV32)"
-description = """assert message:
-qemu/tcg/tcg-op-gvec.c:1714: tcg_gen_gvec_dup_i32: Assertion `vece <= MO_32' failed.
-
-For a e64 vmv.v.x, in the file trans_rvv.c.inc, function "trans_vmv_v_x", when s->vl_eq_vlmax is true, then "tcg_gen_gvec_dup_tl" (it's defined to tcg_gen_gvec_dup_i32 for RV32) is called. In "tcg_gen_gvec_dup_i32" the assert "tcg_debug_assert(vece <= MO_32) will be triggered, since vece == MO_64 for e64."""
-reproduce = """1.enable cfg.Zve64f
-
-2.Prepare a problem as set e64, vl == vl_max and use vmv.v.x, maybe as below
-```
-  li t0, -1,
-  vsetvli x0, t0, e64,m1,tu,mu
-  li t1, -1
-  vmv.v.x v0, t1
-```"""
-additional = """Below is a possible solution if it's appropriate.
-```
-#if TARGET_LONG_BITS == 32
-            if (s->sew == 3) {
-                TCGv_i64 s1_i64 = tcg_temp_new_i64();
-                tcg_gen_ext_tl_i64(s1_i64, s1);
-                tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
-                                     MAXSZ(s), MAXSZ(s), s1_i64);
-                tcg_temp_free_i64(s1_i64);
-            } else {
-#endif
-            tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
-                                MAXSZ(s), MAXSZ(s), s1);
-#if TARGET_LONG_BITS == 32
-            }
-#endif
-```"""