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Diffstat (limited to 'gitlab/issues/target_riscv/host_missing/accel_TCG/1587.toml')
| -rw-r--r-- | gitlab/issues/target_riscv/host_missing/accel_TCG/1587.toml | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/gitlab/issues/target_riscv/host_missing/accel_TCG/1587.toml b/gitlab/issues/target_riscv/host_missing/accel_TCG/1587.toml new file mode 100644 index 00000000..96766678 --- /dev/null +++ b/gitlab/issues/target_riscv/host_missing/accel_TCG/1587.toml @@ -0,0 +1,33 @@ +id = 1587 +title = "Invalid memory access allowed (possibly due to TLB bypassing PMP after mret)" +state = "closed" +created_at = "2023-04-08T20:36:34.624Z" +closed_at = "2023-05-17T05:06:35.011Z" +labels = ["accel: TCG", "target: riscv"] +url = "https://gitlab.com/qemu-project/qemu/-/issues/1587" +host-os = "Fedora 37" +host-arch = "Host: x86-64, Guest: RISCV64" +qemu-version = "QEMU emulator version 7.2.93 (v8.0.0-rc3-dirty)" +guest-os = "Bare metal" +guest-arch = "RISC-V 64" +description = """A load instruction that should be blocked by PMP due to MPRV changing the effective privilege mode to U is allowed. The sequence that I observed was: + + +1. Be in machine mode. +2. Set MPP to U (0). +3. Set MPRV to 1. +4. Enter an ISR, setting MPP to M (3). +5. Load from address xxxx (populating the QEMU TLB). +6. Execute mret, setting MPP back to U (0). +7. Load from address xxxx, which should fail but succeeds without any TLB fill.""" +reproduce = """``` +git clone https://github.com/dreiss/qemu_pmp_repro +cd qemu_pmp_repro +./build_and_run.sh +``` +The `build_and_run.sh` script expects `riscv-none-elf-gcc` and `qemu-system-riscv64` on PATH. It will also attempt to run the reproducer with `spike`, the reference RISC-V emulator, which succeeds.""" +additional = """Adding a call to `tlb_flush` to `helper_mret` causes this test to pass in QEMU, but I don't know if that's a valid fix. + +Output from `build_and_run.sh`: + +[output.txt](/uploads/108547bcb160a8f0bfffe72ea77b215f/output.txt)""" |