summary refs log tree commit diff stats
path: root/gitlab/issues/target_riscv/host_missing/accel_missing/1447.toml
diff options
context:
space:
mode:
Diffstat (limited to 'gitlab/issues/target_riscv/host_missing/accel_missing/1447.toml')
-rw-r--r--gitlab/issues/target_riscv/host_missing/accel_missing/1447.toml19
1 files changed, 19 insertions, 0 deletions
diff --git a/gitlab/issues/target_riscv/host_missing/accel_missing/1447.toml b/gitlab/issues/target_riscv/host_missing/accel_missing/1447.toml
new file mode 100644
index 00000000..e69ff5a4
--- /dev/null
+++ b/gitlab/issues/target_riscv/host_missing/accel_missing/1447.toml
@@ -0,0 +1,19 @@
+id = 1447
+title = "riscv: reset_vec uses CSR even when disabled causing inability to boot"
+state = "closed"
+created_at = "2023-01-17T16:40:23.220Z"
+closed_at = "2023-02-07T20:12:33.668Z"
+labels = ["kind::Bug", "target: riscv"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1447"
+host-os = "N/A"
+host-arch = "N/A"
+qemu-version = "used: 7.2.50"
+guest-os = "n/a"
+guest-arch = "n/a"
+description = "n/a"
+reproduce = """1. Run any rv32 binary with `./qemu-system-riscv32 -cpu rv32,d=off,f=off,Zicsr=off`
+
+To view using GDB use `./qemu-system-riscv32 -cpu rv32,d=off,f=off,Zicsr=off -S -s`
+`gdb-multiarch --ex="target remote localhost:1234" -ex "layout asm"`
+then type `si` till $pc jumps to zero on `csrr   a0, mhartid`"""
+additional = "n/a"