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diff --git a/gitlab/issues/target_riscv/host_missing/accel_missing/1978.toml b/gitlab/issues/target_riscv/host_missing/accel_missing/1978.toml
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+id = 1978
+title = "sifive_e : erroneous CLINT frequency"
+state = "closed"
+created_at = "2023-11-10T15:31:26.868Z"
+closed_at = "2023-11-22T16:50:14.424Z"
+labels = ["target: riscv"]
+url = "https://gitlab.com/qemu-project/qemu/-/issues/1978"
+host-os = "MacOS Sonoma"
+host-arch = "Arm"
+qemu-version = "QEMU emulator version 8.1.2"
+guest-os = "Bare metal"
+guest-arch = "RISCV32"
+description = """CLINT's `mtime` updates at a clock frequency of [10 MHz](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/riscv/sifive_e.c?ref_type=heads#L228), whereas [SiFive documentation](https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf?_gl=1*w2ieef*_ga*MTcyNDI2MjM0Ny4xNjk2ODcwNTM3*_ga_T369JS7J9N*MTY5Njg3MDUzNy4xLjAuMTY5Njg3MDUzNy42MC4wLjA.) shows that its clock frequency is 32.768 kHz (i.e., the RTC clock).
+
+This difference leads to unexpected timing behavior. Due to the difference, it can even trigger multiple nested interrupts as the IRQ routine is not able to return before a new timer interrupt is triggered."""
+reproduce = "n/a"
+additional = "n/a"