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diff --git a/gitlab/issues/target_riscv/host_missing/accel_missing/2463.toml b/gitlab/issues/target_riscv/host_missing/accel_missing/2463.toml
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-id = 2463
-title = "allow sifive_e to use more RAM"
-state = "closed"
-created_at = "2024-07-27T16:38:41.790Z"
-closed_at = "2024-08-13T02:27:24.981Z"
-labels = ["target: riscv"]
-url = "https://gitlab.com/qemu-project/qemu/-/issues/2463"
-host-os = "Ubuntu23"
-host-arch = "x86"
-qemu-version = "git july 26 2024"
-guest-os = "none, bare-metal, no-libc"
-guest-arch = "riscv rv32g"
-description = """For users like me that are still learning RISC bare-metal assembly, searching online you will find many tutorials and examples using sifive_e with Qemu, so it is the easy way to get started.
-
-I quickly ran into crashes with my tests because I did not realize that sifive_e is limited to 16K of RAM.
-I realize the 16K limit is hard coded so that it matches the real hardware, but that makes it very hard to run a variety of tests."""
-reproduce = "n/a"
-additional = """My fork of Qemu changes sifive_e to allow 256MB.
-https://github.com/panjea/qemu/commit/97cb89d778ebe3407a969b8282e2e7adb4be2971"""