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+arm: 0.954
+kernel: 0.840
+semantic: 0.780
+device: 0.738
+ppc: 0.719
+architecture: 0.705
+socket: 0.693
+performance: 0.686
+network: 0.620
+vnc: 0.608
+permissions: 0.603
+debug: 0.567
+peripherals: 0.545
+files: 0.544
+PID: 0.543
+graphic: 0.542
+register: 0.538
+user-level: 0.532
+boot: 0.517
+risc-v: 0.517
+TCG: 0.468
+mistranslation: 0.452
+x86: 0.429
+hypervisor: 0.423
+virtual: 0.421
+VMM: 0.416
+i386: 0.409
+KVM: 0.343
+assembly: 0.245
+
+qemu-system-arm exits when cortex-m4 floating point used and irq occurs
+
+qemu-system-arm exits with 
+
+"...Secure UsageFault with CFSR.NOCP because NSACR.CP10 prevents stacking FP regs
+...taking pending nonsecure exception 3
+Taking exception 7 [Breakpoint]
+qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)" 
+
+when emulating Cortex-m4, executing at least 1 floating point instruction, and then an irq (e.g. sys tick) occurring.
+
+CPACR.CP10 and CPACR.CP11 are set to 0x3 respectively prior to executing the fp instructions.
+
+NOTE: NSACR does not appear to be a cortex m4 register.
+
+Attached is a simplified elf to repro the issue.
+
+The qemu command line is: "qemu-system-arm --gdb tcp::1234 -cpu cortex-m4 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel QemuExitWhenUsingFPAndIRQOccurs.elf -d int"
+
+
+
+I think this patch should fix this bug:
+
+https://<email address hidden>/
+
+
+I confirm that this fixes the issue above.
+
+Thank you for your help! It is much appreciated.
+
+Now fixed in git master; will be in the imminent 4.1 release.
+
+
+https://git.qemu.org/?p=qemu.git;a=commitdiff;h=02ac2f7f613b47f6a5b3
+