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Diffstat (limited to 'results/classifier/accel-gemma3:12b/tcg/1923629')
| -rw-r--r-- | results/classifier/accel-gemma3:12b/tcg/1923629 | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/results/classifier/accel-gemma3:12b/tcg/1923629 b/results/classifier/accel-gemma3:12b/tcg/1923629 new file mode 100644 index 00000000..ab13174b --- /dev/null +++ b/results/classifier/accel-gemma3:12b/tcg/1923629 @@ -0,0 +1,14 @@ + +RISC-V Vector Instruction vssub.vv not saturating + +I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF). + +Here is the bit of the code: + + vmv.v.i v16, 0 + … +8f040457 vssub.vv v8,v16,v8 + +I believe the instruction encoding is correct (vssub.vv with vd = v8, vs2 = v16, rs1 = v8), but the result does not saturate in QEMU. + +I’ve just tested with what I think is the latest branch ( https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb 2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still exists. \ No newline at end of file |