summary refs log tree commit diff stats
path: root/results/classifier/accel-gemma3:12b/tcg/2717
diff options
context:
space:
mode:
Diffstat (limited to 'results/classifier/accel-gemma3:12b/tcg/2717')
-rw-r--r--results/classifier/accel-gemma3:12b/tcg/271713
1 files changed, 13 insertions, 0 deletions
diff --git a/results/classifier/accel-gemma3:12b/tcg/2717 b/results/classifier/accel-gemma3:12b/tcg/2717
new file mode 100644
index 00000000..9ed7bb99
--- /dev/null
+++ b/results/classifier/accel-gemma3:12b/tcg/2717
@@ -0,0 +1,13 @@
+
+semihosting link to risc-v details in document is changed
+Description of problem:
+
+Steps to reproduce:
+1. Open https://gitlab.com/qemu-project/qemu/-/blob/master/docs/about/emulation.rst
+2. Goto Supported Targets section
+3. Click RISC-V link in the table
+4. Got 404
+
+New url looks like https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc
+Additional information:
+