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Diffstat (limited to 'results/classifier/gemma3:12b/assembly/996798')
| -rw-r--r-- | results/classifier/gemma3:12b/assembly/996798 | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/results/classifier/gemma3:12b/assembly/996798 b/results/classifier/gemma3:12b/assembly/996798 new file mode 100644 index 00000000..ced953bb --- /dev/null +++ b/results/classifier/gemma3:12b/assembly/996798 @@ -0,0 +1,12 @@ + +Incorrect order of task switching + +In Intel specifications (http://download.intel.com/design/processor/manuals/253668.pdf 7.3), we can see: + + 8. Saves the state of the current (old) task in the current task’s TSS. + +… + + 11. Loads the task register with the segment selector and descriptor for the new task's TSS. + +But, in QEMU code (https://raw.github.com/qemu/QEMU/v1.0/target-i386/op_helper.c :375), the order is reversed: TSS registers & segments loads BEFORE save old task state. \ No newline at end of file |