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-rw-r--r--results/classifier/semantic-bugs/157434631
1 files changed, 2 insertions, 29 deletions
diff --git a/results/classifier/semantic-bugs/1574346 b/results/classifier/semantic-bugs/1574346
index 410bb5ba..48895310 100644
--- a/results/classifier/semantic-bugs/1574346
+++ b/results/classifier/semantic-bugs/1574346
@@ -1,15 +1,4 @@
-instruction: 0.779
-other: 0.750
-graphic: 0.731
-device: 0.728
-mistranslation: 0.635
-semantic: 0.551
-network: 0.544
-socket: 0.467
-vnc: 0.421
-boot: 0.390
-assembly: 0.341
-KVM: 0.339
+
 
 TCG: mov to segment register is incorrectly emulated for AMD CPUs
 
@@ -22,20 +11,4 @@ is to mark the GS segment unusable and set its base to zero.  After doing this,
 
 This is correct for Intel CPUs but is incorrect for AMD CPUs.  On an AMD CPU, writing 0 to %gs using mov, pop, or (I think) lgs will leave the base unchanged.
 
-To make it easier to use TCG to validate behavior on different CPUs, please consider changing the TCG behavior to match actual CPU behavior when emulating an AMD CPU.
-
-The QEMU project is currently considering to move its bug tracking to
-another system. For this we need to know which bugs are still valid
-and which could be closed already. Thus we are setting older bugs to
-"Incomplete" now.
-
-If you still think this bug report here is valid, then please switch
-the state back to "New" within the next 60 days, otherwise this report
-will be marked as "Expired". Or please mark it as "Fix Released" if
-the problem has been solved with a newer version of QEMU already.
-
-Thank you and sorry for the inconvenience.
-
-
-[Expired for QEMU because there has been no activity for 60 days.]
-
+To make it easier to use TCG to validate behavior on different CPUs, please consider changing the TCG behavior to match actual CPU behavior when emulating an AMD CPU.
\ No newline at end of file