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Diffstat (limited to 'results/classifier/semantic-bugs/instruction/1574346')
| -rw-r--r-- | results/classifier/semantic-bugs/instruction/1574346 | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/results/classifier/semantic-bugs/instruction/1574346 b/results/classifier/semantic-bugs/instruction/1574346 deleted file mode 100644 index 410bb5ba..00000000 --- a/results/classifier/semantic-bugs/instruction/1574346 +++ /dev/null @@ -1,41 +0,0 @@ -instruction: 0.779 -other: 0.750 -graphic: 0.731 -device: 0.728 -mistranslation: 0.635 -semantic: 0.551 -network: 0.544 -socket: 0.467 -vnc: 0.421 -boot: 0.390 -assembly: 0.341 -KVM: 0.339 - -TCG: mov to segment register is incorrectly emulated for AMD CPUs - -In TCG mode, the effect of: - -xorl %eax, %eax -movl %eax, %gs - -is to mark the GS segment unusable and set its base to zero. After doing this, reading MSR_GS_BASE will return zero and using a GS prefix in long mode will treat the GS base as zero. - -This is correct for Intel CPUs but is incorrect for AMD CPUs. On an AMD CPU, writing 0 to %gs using mov, pop, or (I think) lgs will leave the base unchanged. - -To make it easier to use TCG to validate behavior on different CPUs, please consider changing the TCG behavior to match actual CPU behavior when emulating an AMD CPU. - -The QEMU project is currently considering to move its bug tracking to -another system. For this we need to know which bugs are still valid -and which could be closed already. Thus we are setting older bugs to -"Incomplete" now. - -If you still think this bug report here is valid, then please switch -the state back to "New" within the next 60 days, otherwise this report -will be marked as "Expired". Or please mark it as "Fix Released" if -the problem has been solved with a newer version of QEMU already. - -Thank you and sorry for the inconvenience. - - -[Expired for QEMU because there has been no activity for 60 days.] - |