diff options
Diffstat (limited to 'results/classifier/zero-shot-user-mode/instruction/1611394')
| -rw-r--r-- | results/classifier/zero-shot-user-mode/instruction/1611394 | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/results/classifier/zero-shot-user-mode/instruction/1611394 b/results/classifier/zero-shot-user-mode/instruction/1611394 new file mode 100644 index 00000000..0b375188 --- /dev/null +++ b/results/classifier/zero-shot-user-mode/instruction/1611394 @@ -0,0 +1,35 @@ +instruction: 0.570 +runtime: 0.229 +syscall: 0.201 + + + +qemu-ppc: Scalar Single-Precision Floating-Point instructions should not test MSR[SPV] + +According to "Signal Processing Engine (SPE) Programming Environments Manual" at +http://cache.nxp.com/files/32bit/doc/ref_manual/SPEPEM.pdf?fsrch=1&sr=1&pageNum=1 + +c.f section 4.2.3 and also Figure 2-2. + +When MSR[SPV] is _NOT_ set, then the embedded scalar single-precision floating-point instructions +should _NOT_ generate an Embedded Floating-Point Unavailable Interrupt. + + +Hence, some tests for MSR[SPV] in file target-ppc/translate.c need to be removed. +Namely, in the definitions of +1. GEN_SPEFPUOP_ARITH2_32_32 +2. gen_efsabs +3. gen_efsnabs +4. gen_efsneg +5. GEN_SPEFPUOP_COMP_32 + +Note, the macro GEN_SPEFPUOP_CONV_32_32 is already correct. + +One more thing, afaict the macro GEN_SPEFPUOP_CONV_32_64 is used by both +efs- and efd- instructions, and will need to be split in two versions. +The efs-use (i.e for efscfd) should be as it is today, but the use by efd-instructions +(e.g efdctui) will need to add a test for MSR[SPV]. + + + +(I've looked at today's HEAD-revision of target-ppc/translate.c). \ No newline at end of file |