diff options
Diffstat (limited to 'results/classifier/zero-shot/108/other/2796')
| -rw-r--r-- | results/classifier/zero-shot/108/other/2796 | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/results/classifier/zero-shot/108/other/2796 b/results/classifier/zero-shot/108/other/2796 new file mode 100644 index 00000000..c9c6793e --- /dev/null +++ b/results/classifier/zero-shot/108/other/2796 @@ -0,0 +1,22 @@ +device: 0.832 +graphic: 0.731 +other: 0.490 +performance: 0.485 +semantic: 0.482 +vnc: 0.357 +PID: 0.285 +permissions: 0.282 +debug: 0.269 +socket: 0.257 +boot: 0.242 +files: 0.183 +network: 0.145 +KVM: 0.013 + +Opentitan Timer ignores COMPARE_UPPER0/COMPARE_LOWER0 +Description of problem: +In a bare metal application, running on an emulated Opentitan board, if you set a timer interrupt threshold by writing to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before writing to `rv_timer.CTRL` to start the timer, then the interrupt does not fire. If you write to the `COMPARE_*` registers *after* starting the timer by writing to `CTRL`, then the interrupt fires correctly. + +I think the explanation is that [ibex_timer_update_irqs](https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L61) has an early return if `rv_timer.CTRL` is not set. As a result, although writes to `COMPARE_*` always call `ibex_timer_update_irqs`, they don't have their intended side-effects before `CTRL` is unset. +Steps to reproduce: +Write to `rv_timer.COMPARE_UPPER0` and `rv_timer.COMPARE_LOWER0` before you have set `rv_timer.CTRL`. Observe that no timer interrupt occurs. |