blob: a5d625d423d747e9bb6cc01cb2cea0214f29307e (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
|
Incorrect RNG_CTRL and RNG_DATA_OUTPUT register offets for Aspeed AST2600 A3
Description of problem:
hw/misc/aspeed_scu.c has the following lines:
#define AST2600_RNG_CTRL TO_REG(0x524)
#define AST2600_RNG_DATA TO_REG(0x540)
The Datasheet for the AST2600 A3 lists the offsets as 0x520 for RNG_CTRL and 0x524 for RNG_DATA. I can confirm that these addresses are correct on the hardware. I don't know if the offsets changed from a previous revision, but since qemu fills the SILICON_REV register with the AST2600_A3_SILICON_REV value for the AST2600, it makes sense to me that it would use the A3 register offsets.
Steps to reproduce:
1.
2.
3.
Additional information:
|