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graphic: 0.829
mistranslation: 0.779
device: 0.742
semantic: 0.708
other: 0.610
network: 0.604
vnc: 0.535
instruction: 0.397
boot: 0.303
socket: 0.199
KVM: 0.037
assembly: 0.003
Opentitan timer layout incorrect
Description of problem:
It looks as if some of the timer register offsets here are incorrect:
https://gitlab.com/qemu-project/qemu/-/blob/master/hw/timer/ibex_timer.c?ref_type=heads#L37
Compare with:
https://opentitan.org/book/hw/ip/rv_timer/doc/registers.html
I suspect they're out of date. The documentation link on line 7 is not working anymore - the current documentation URL for Opentitan is the one just given.
It might also make sense to rename this file `opentitan_timer.c`, instead of `ibex_timer.c`. The timer is an Opentitan hardware IP block, rather than a feature of the Ibex CPU.
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