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semantic: 0.665
other: 0.660
graphic: 0.553
device: 0.484
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debug: 0.341
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KVM: 0.130
qemu-i386 pentium3/athlon incorrect instruction set
Running a binary containing a movsd instruction (SSE2) in 32-bit qemu-i386 -cpu pentium3 from 20150609 results in flawless execution whereas it should crash with SIGILL as P3 only had SSE.
Still there in the latest master.
To clarify, running the binary with the -cpu athlon switch (same instruction set as P3) also exhibits the problem whereas a real athlon SIGILL's correctly.
QEMU doesn't try to mimic the exact set of instructions for a processor, unfortunately. Virtualization solutions like KVM also do not allow you to do that, so the case for this feature is relatively minor.
However, patches are welcome.
I'm pretty sure you're right regarding entire instruction sets - but surely simply disabling SSE2 is possible even now? (after all pentium2 and below doesn't have it)
That could solve this problem with a simple hack like, eg. :
pentium3 = $pentium3 - SSE2
In the case it's really unfixable and both pentium3 and athlon are nothing more than aliases for 'QEMU Virtual CPU version 2.4.50' they should be removed from the list the user gets after:
qemu-i386 -cpu help
so as not to mislead. Thanks!
After looking at target-i386/cpu.c, it's clear to me CPUID_SSE and CPUID_SSE2 are defined seperately and neither pentium3 nor athlon have those defines set.
This could mean it's a bug not in the instruction set but possibly in the build process somewhere.
This option is useful for testing, nothing more.
I think I may have found the culprit - athlon is defined as 'PPRO_FEATURES + some additional features'.
If PPRO_FEATURES is what I think it is (pentium pro) why does it have SSE and SSE2 defined? It should end with MMX.
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