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graphic: 0.779
performance: 0.718
device: 0.706
other: 0.701
semantic: 0.633
vnc: 0.621
network: 0.540
PID: 0.448
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Variation of SVE register size (qemu-user-aarch64)
Specification of ARMv8-A SVE extention allows various values for the size of the SVE register. On the other hand, it seems that the current qemu-aarch64 supports only the maximum length of 2048 bits as the SVE register size. I am writing an assembler program for a CPU that is compliant with ARMv8-A + SVE and has a 512-bit SVE register, but when this is run with qemu-user-aarch64, a 2048-bit load / store instruction is executed This causes a segmentation fault. Shouldn't qeum-user-aarch64 have an option to specify the SVE register size?
This is already managed by a cpu property.
0df9142d27d5 ("target/arm/cpu64: max cpu: Introduce sve<N> properties")
See docs/arm-cpu-features.rst
Try "-cpu max,sve512=on".
Note also that the vector length in SVE is not fixed -- you should be writing your guest code to support arbitrary vector lengths, because otherwise it will not run on all SVE-supporting CPUs.
Thank you for your kind advice. I'll try it.
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