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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-05-05 23:13:12 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2018-05-14 10:29:27 +0200 |
| commit | 94d49ed54f07e3d399de74de13f5422837c031fa (patch) | |
| tree | b3f7fd34c7ff8d17bd9f26d53511b30935485092 /example/expression/get_read_write.py | |
| parent | db4fd7f58d6a4ed87fc7d6f28c7c2af31e61fb65 (diff) | |
| download | focaccia-miasm-94d49ed54f07e3d399de74de13f5422837c031fa.tar.gz focaccia-miasm-94d49ed54f07e3d399de74de13f5422837c031fa.zip | |
Core: updt parser structure
Diffstat (limited to 'example/expression/get_read_write.py')
| -rw-r--r-- | example/expression/get_read_write.py | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/example/expression/get_read_write.py b/example/expression/get_read_write.py index d107cfa2..9e3b5caf 100644 --- a/example/expression/get_read_write.py +++ b/example/expression/get_read_write.py @@ -1,6 +1,9 @@ from miasm2.arch.x86.arch import mn_x86 from miasm2.expression.expression import get_rw from miasm2.arch.x86.ira import ir_a_x86_32 +from miasm2.core.asmblock import AsmSymbolPool + +symbol_pool = AsmSymbolPool() print """ @@ -11,7 +14,7 @@ Get read/written registers for a given instruction arch = mn_x86 ir_arch = ir_a_x86_32() -l = arch.fromstring('LODSB', 32) +l = arch.fromstring('LODSB', symbol_pool, 32) l.offset, l.l = 0, 15 ir_arch.add_instr(l) |