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| author | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
|---|---|---|
| committer | Fabrice Desclaux <fabrice.desclaux@cea.fr> | 2014-09-05 11:30:05 +0200 |
| commit | 6e09df71a333bf87cd68c2d08ad068a3e501462d (patch) | |
| tree | 7d76e0626e61ef5a9f15c62358337674fb0095aa /miasm2/jitter/jitcore_python.py | |
| parent | e8d0fcf8d28d82a8f33138d044f335634ac3a30c (diff) | |
| download | focaccia-miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.tar.gz focaccia-miasm-6e09df71a333bf87cd68c2d08ad068a3e501462d.zip | |
Modify irbloc destination mecanism. Rework API in consequence.
Fat patch here: some API have changed. Each irbloc now affects a special "IRDst" register which is used to describe the destination irbloc. It allows simple description of architectures using delay slots. Architectures semantic and tcc/python jitter are modified in consequence. LLVM jitter is disabled for now, but should be patch soon.
Diffstat (limited to 'miasm2/jitter/jitcore_python.py')
| -rw-r--r-- | miasm2/jitter/jitcore_python.py | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/miasm2/jitter/jitcore_python.py b/miasm2/jitter/jitcore_python.py index 90c8bace..c2fb4be1 100644 --- a/miasm2/jitter/jitcore_python.py +++ b/miasm2/jitter/jitcore_python.py @@ -49,18 +49,19 @@ def update_engine_from_cpu(cpu, exec_engine): class JitCore_Python(jitcore.JitCore): "JiT management, using Miasm2 Symbol Execution engine as backend" - def __init__(self, my_ir, bs=None): - super(JitCore_Python, self).__init__(my_ir, bs) + def __init__(self, ir_arch, bs=None): + super(JitCore_Python, self).__init__(ir_arch, bs) self.symbexec = None + self.ir_arch = ir_arch - def load(self, arch): + def load(self): "Preload symbols according to current architecture" symbols_init = {} - for i, r in enumerate(arch.regs.all_regs_ids_no_alias): - symbols_init[r] = arch.regs.all_regs_ids_init[i] + for i, r in enumerate(self.ir_arch.arch.regs.all_regs_ids_no_alias): + symbols_init[r] = self.ir_arch.arch.regs.all_regs_ids_init[i] - self.symbexec = symbexec(arch, symbols_init, + self.symbexec = symbexec(self.ir_arch, symbols_init, func_read = self.func_read, func_write = self.func_write) @@ -157,7 +158,7 @@ class JitCore_Python(jitcore.JitCore): return line.offset # Get next bloc address - ad = expr_simp(exec_engine.eval_expr(irb.dst)) + ad = expr_simp(exec_engine.eval_expr(self.ir_arch.IRDst)) # Updates @cpu instance according to new CPU values update_cpu_from_engine(cpu, exec_engine) |