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| author | BALATON Zoltan <balaton@eik.bme.hu> | 2018-06-29 00:38:33 +0200 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-07-03 11:13:08 +1000 |
| commit | 0123d3cbb06600e0624fdbf2255055d9cffe9c28 (patch) | |
| tree | 96fe9f053b51e78a06a68132be7c85c03a555722 | |
| parent | 2a8ceefca23bc2aaafe711f8afd7585be3c27064 (diff) | |
| download | focaccia-qemu-0123d3cbb06600e0624fdbf2255055d9cffe9c28.tar.gz focaccia-qemu-0123d3cbb06600e0624fdbf2255055d9cffe9c28.zip | |
target/ppc: Relax reserved bitmask of indexed store instructions
The PPC440 User Manual says that if bit 31 is set, the contents of CR[CR0] are undefined for indexed store instructions but this form is not invalid. Other PPC variants confirming to recent ISA where this bit may be reserved should ignore reserved bits and not raise invalid instruction exception. In particular, MorphOS has an stwx instruction with bit 31 set and fails to boot currently because of this. With this patch it gets further. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| -rw-r--r-- | target/ppc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 65c8cc94e7..9eaa10b421 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7054,7 +7054,7 @@ GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), #define GEN_STUX(name, stop, opc2, opc3, type) \ GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ -GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), +GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), #define GEN_STS(name, stop, op, type) \ GEN_ST(name, stop, op | 0x20, type) \ GEN_STU(name, stop, op | 0x21, type) \ |