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authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>2014-09-29 18:48:49 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-09-29 18:48:49 +0100
commit043b7f8d12dc922172cf7d570dc2854dbf81dcb3 (patch)
tree1565f450a12dd17d0a097a3bb6760c8c180e4c3b
parent9e729b57ac2a3adebee2746a2106a70eb8230a72 (diff)
downloadfocaccia-qemu-043b7f8d12dc922172cf7d570dc2854dbf81dcb3.tar.gz
focaccia-qemu-043b7f8d12dc922172cf7d570dc2854dbf81dcb3.zip
target-arm: Break out exception masking to a separate func
Reviewed-by: Greg Bellows <greg.bellows@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-5-git-send-email-edgar.iglesias@gmail.com
[PMM: updated to account for recent cpu-exec refactoring]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target-arm/cpu.c7
-rw-r--r--target-arm/cpu.h15
2 files changed, 17 insertions, 5 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 248778d57a..b7cdcd7c7a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -187,12 +187,10 @@ static void arm_cpu_reset(CPUState *s)
 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 {
     CPUClass *cc = CPU_GET_CLASS(cs);
-    ARMCPU *cpu = ARM_CPU(cs);
-    CPUARMState *env = &cpu->env;
     bool ret = false;
 
     if (interrupt_request & CPU_INTERRUPT_FIQ
-        && !(env->daif & PSTATE_F)) {
+        && arm_excp_unmasked(cs, EXCP_FIQ)) {
         cs->exception_index = EXCP_FIQ;
         cc->do_interrupt(cs);
         ret = true;
@@ -207,8 +205,7 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
        We avoid this by disabling interrupts when
        pc contains a magic address.  */
     if (interrupt_request & CPU_INTERRUPT_HARD
-        && !(env->daif & PSTATE_I)
-        && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
+        && arm_excp_unmasked(cs, EXCP_IRQ)) {
         cs->exception_index = EXCP_IRQ;
         cc->do_interrupt(cs);
         ret = true;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a3ba624b74..cc2c2100b3 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1172,6 +1172,21 @@ bool write_cpustate_to_list(ARMCPU *cpu);
 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
 #endif
 
+static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx)
+{
+    CPUARMState *env = cs->env_ptr;
+
+    switch (excp_idx) {
+    case EXCP_FIQ:
+        return !(env->daif & PSTATE_F);
+    case EXCP_IRQ:
+        return !(env->daif & PSTATE_I)
+               && (!IS_M(env) || env->regs[15] < 0xfffffff0);
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static inline CPUARMState *cpu_init(const char *cpu_model)
 {
     ARMCPU *cpu = cpu_arm_init(cpu_model);