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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-06-02 11:51:48 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-06-02 11:51:48 +0100 |
| commit | 06312febfb2d35367006ef23608ddd6a131214d4 (patch) | |
| tree | 9e849bdaa9b3fe34d433851ce15335d2437c4115 | |
| parent | f50cd31413d8bc9d1eef8edd1f878324543bf65d (diff) | |
| download | focaccia-qemu-06312febfb2d35367006ef23608ddd6a131214d4.tar.gz focaccia-qemu-06312febfb2d35367006ef23608ddd6a131214d4.zip | |
arm: Don't let no-MPU PMSA cores write to SCTLR.M
If the CPU is a PMSA config with no MPU implemented, then the SCTLR.M bit should be RAZ/WI, so that the guest can never turn on the non-existent MPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1493122030-32191-7-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/helper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 404bfdb439..f0f25c8ee8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3258,6 +3258,11 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { + /* M bit is RAZ/WI for PMSA with no MPU implemented */ + value &= ~SCTLR_M; + } + raw_write(env, ri, value); /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */ |