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| author | Cao jin <caoj.fnst@cn.fujitsu.com> | 2016-05-17 09:41:18 +0800 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2016-06-07 18:19:23 +0300 |
| commit | 0668a06b81bb709b72aa816083227eb0d44b2ad6 (patch) | |
| tree | c5d3c280b3c1f12e7b625f87629d19d92fbabd6d | |
| parent | bbd908025c530b57f57b5c5b739d53e28c1e59fc (diff) | |
| download | focaccia-qemu-0668a06b81bb709b72aa816083227eb0d44b2ad6.tar.gz focaccia-qemu-0668a06b81bb709b72aa816083227eb0d44b2ad6.zip | |
ICH9: fix typo
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
| -rw-r--r-- | hw/isa/lpc_ich9.c | 4 | ||||
| -rw-r--r-- | include/hw/i386/ich9.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 2a2d52e69a..213741bc21 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -97,8 +97,8 @@ static void ich9_cc_update(ICH9LPCState *lpc) /* * D30: DMI2PCI bridge - * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge - * are connected to pirq lines. Our choice is PIRQ[E-H]. + * It is arbitrarily decided how INTx lines of PCI devices behind + * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. * INT[A-D] are connected to PIRQ[E-H] */ for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index d04dcdcfb3..88233c3077 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -35,7 +35,7 @@ typedef struct ICH9LPCState { /* (pci device, intx) -> pirq * In real chipset case, the unused slots are never used - * as ICH9 supports only D25-D32 irq routing. + * as ICH9 supports only D25-D31 irq routing. * On the other hand in qemu case, any slot/function can be populated * via command line option. * So fallback interrupt routing for any devices in any slots is necessary. @@ -181,7 +181,7 @@ Object *ich9_lpc_find(void); #define ICH9_SATA1_DEV 31 #define ICH9_SATA1_FUNC 2 -/* D30:F1 power management I/O registers +/* D31:F0 power management I/O registers offset from the address ICH9_LPC_PMBASE */ /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ |