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| author | Cédric Le Goater <clg@kaod.org> | 2018-06-26 17:50:39 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-06-26 17:50:39 +0100 |
| commit | 0721309ed77100e857a7149dd563a4d1a0d07d68 (patch) | |
| tree | 4e3b2a4e709e3379535081a2e7cd96f818598662 | |
| parent | 0ab4c574a55448a37b9f616259b82950742c9427 (diff) | |
| download | focaccia-qemu-0721309ed77100e857a7149dd563a4d1a0d07d68.tar.gz focaccia-qemu-0721309ed77100e857a7149dd563a4d1a0d07d68.zip | |
aspeed/smc: fix dummy cycles count when in dual IO mode
When configured in dual I/O mode, address and data are sent in dual mode, including the dummy byte cycles in between. Adapt the count to the IO setting. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180612065716.10587-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/ssi/aspeed_smc.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 5059396bc6..fce126e6ee 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -66,6 +66,8 @@ /* CEx Control Register */ #define R_CTRL0 (0x10 / 4) +#define CTRL_IO_DUAL_DATA (1 << 29) +#define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ #define CTRL_CMD_SHIFT 16 #define CTRL_CMD_MASK 0xff #define CTRL_DUMMY_HIGH_SHIFT 14 @@ -492,8 +494,13 @@ static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl) uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->id]; uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; + uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8; - return ((dummy_high << 2) | dummy_low) * 8; + if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) { + dummies /= 2; + } + + return dummies; } static void aspeed_smc_flash_send_addr(AspeedSMCFlash *fl, uint32_t addr) |