summary refs log tree commit diff stats
diff options
context:
space:
mode:
authorPeter Maydell <peter.maydell@linaro.org>2015-04-26 16:49:25 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-04-26 16:49:25 +0100
commit0995bf8cd91b81ec9c1078e37b808794080dc5c0 (patch)
tree62c82605c1abae5c2f46592d74c031652579d2c3
parentebca90e4c3aaaae5ed1ee7c569dea00d5d6ed476 (diff)
downloadfocaccia-qemu-0995bf8cd91b81ec9c1078e37b808794080dc5c0.tar.gz
focaccia-qemu-0995bf8cd91b81ec9c1078e37b808794080dc5c0.zip
target-arm: Add user-mode transaction attribute
Add a transaction attribute indicating that a memory access is being
done from user-mode (unprivileged). This corresponds to an equivalent
signal in ARM AMBA buses.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-rw-r--r--include/exec/memattrs.h2
-rw-r--r--target-arm/helper.c1
2 files changed, 3 insertions, 0 deletions
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 68a9c760d5..1389b4b01d 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -31,6 +31,8 @@ typedef struct MemTxAttrs {
     unsigned int unspecified:1;
     /* ARM/AMBA TrustZone Secure access */
     unsigned int secure:1;
+    /* Memory access is usermode (unprivileged) */
+    unsigned int user:1;
 } MemTxAttrs;
 
 /* Bus masters which don't specify any attributes will get this,
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a01ff7fccc..50469cdae0 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5749,6 +5749,7 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address,
      * to secure.
      */
     attrs->secure = regime_is_secure(env, mmu_idx);
+    attrs->user = regime_is_user(env, mmu_idx);
 
     /* Fast Context Switch Extension. This doesn't exist at all in v8.
      * In v7 and earlier it affects all stage 1 translations.