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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-24 13:17:46 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-24 13:17:46 +0100 |
| commit | 139d941e5a61d29c895ab422031eb7fd8797e059 (patch) | |
| tree | 97ee97fbbadf1de2a6ba6aad9599a5a9a85d12c2 | |
| parent | 13391a563fc4048736d259b685676b02dd0ba52d (diff) | |
| download | focaccia-qemu-139d941e5a61d29c895ab422031eb7fd8797e059.tar.gz focaccia-qemu-139d941e5a61d29c895ab422031eb7fd8797e059.zip | |
hw/ssi/pl022: Correct wrong value for PL022_INT_RT
The PL022 interrupt registers have bits allocated as: 0: ROR (receive overrun) 1: RT (receive timeout) 2: RX (receive FIFO half full or less) 3: TX (transmit FIFO half full or less) A cut and paste error meant we had the wrong value for the PL022_INT_RT constant. This bug doesn't affect device behaviour, because we don't implement the receive timeout feature and so never set that interrupt bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-20-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | hw/ssi/pl022.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ssi/pl022.c b/hw/ssi/pl022.c index 3ac57f4c96..d310671d18 100644 --- a/hw/ssi/pl022.c +++ b/hw/ssi/pl022.c @@ -38,7 +38,7 @@ do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0) #define PL022_SR_BSY 0x10 #define PL022_INT_ROR 0x01 -#define PL022_INT_RT 0x04 +#define PL022_INT_RT 0x02 #define PL022_INT_RX 0x04 #define PL022_INT_TX 0x08 |