Fix Arm interrupted ldm bug.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1743 c046a42c-6fe2-441c-8c8c-71466251a162

2 files changed, 19 insertions, 1 deletions

diff --git a/target-arm/op.c b/target-arm/op.c
index acac2394a6..f06b06b908 100644
--- a/target-arm/op.c
+++ b/target-arm/op.c
@@ -1181,3 +1181,13 @@ void OPPROTO op_movl_user_T0(void)
     }
     FORCE_RET();
 }
+
+void OPPROTO op_movl_T2_T0(void)
+{
+    T2 = T0;
+}
+
+void OPPROTO op_movl_T0_T2(void)
+{
+    T0 = T2;
+}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 5f817080f8..d5cbc5ee1d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1627,7 +1627,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
         case 0x08:
         case 0x09:
             {
-                int j, n, user;
+                int j, n, user, loaded_base;
                 /* load/store multiple words */
                 /* XXX: store correct base if write back */
                 user = 0;
@@ -1642,6 +1642,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
                 gen_movl_T1_reg(s, rn);
                 
                 /* compute total size */
+                loaded_base = 0;
                 n = 0;
                 for(i=0;i<16;i++) {
                     if (insn & (1 << i))
@@ -1675,6 +1676,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
                                 gen_bx(s);
                             } else if (user) {
                                 gen_op_movl_user_T0(i);
+                            } else if (i == rn) {
+                                gen_op_movl_T2_T0();
+                                loaded_base = 1;
                             } else {
                                 gen_movl_reg_T0(s, i);
                             }
@@ -1718,6 +1722,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
                     }
                     gen_movl_reg_T1(s, rn);
                 }
+                if (loaded_base) {
+                    gen_op_movl_T0_T2();
+                    gen_movl_reg_T0(s, rn);
+                }
                 if ((insn & (1 << 22)) && !user) {
                     /* Restore CPSR from SPSR.  */
                     gen_op_movl_T0_spsr();