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| author | Fea.Wang <fea.wang@sifive.com> | 2024-12-03 11:49:32 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-12-20 11:22:47 +1000 |
| commit | 19d476ff13afbad04c52efb2dff0362839ae510a (patch) | |
| tree | 9eba51d290154ba294c2f485070fa884d76aeda1 | |
| parent | 093c613cb69aa06bf38ce94e3261a0f44f266393 (diff) | |
| download | focaccia-qemu-19d476ff13afbad04c52efb2dff0362839ae510a.tar.gz focaccia-qemu-19d476ff13afbad04c52efb2dff0362839ae510a.zip | |
target/riscv: Check svukte is not enabled in RV32
The spec explicitly says svukte doesn't support RV32. So check that it is not enabled in RV32. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241203034932.25185-7-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/tcg/tcg-cpu.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index c62c221696..3b99c8c9e3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -652,6 +652,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { + error_setg(errp, "svukte is not supported for RV32"); + return; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need. |