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| author | Michael Clark <mjc@sifive.com> | 2018-03-06 10:17:11 +1300 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-05-06 10:39:38 +1200 |
| commit | 1d1ee55274860bfcc511d50d83c84394c2685ba8 (patch) | |
| tree | 5b8815298683e783d0518384359c44fd476be1a1 | |
| parent | 6fce529c4b3ecbff17bbd930f6beaac9a6067114 (diff) | |
| download | focaccia-qemu-1d1ee55274860bfcc511d50d83c84394c2685ba8.tar.gz focaccia-qemu-1d1ee55274860bfcc511d50d83c84394c2685ba8.zip | |
RISC-V: Make mtvec/stvec ignore vectored traps
Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
| -rw-r--r-- | target/riscv/op_helper.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3512462f4f..af0c52a484 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -287,11 +287,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, env->sepc = val_to_write; break; case CSR_STVEC: - if (val_to_write & 1) { + /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ + if ((val_to_write & 3) == 0) { + env->stvec = val_to_write >> 2 << 2; + } else { qemu_log_mask(LOG_UNIMP, "CSR_STVEC: vectored traps not supported"); - goto do_illegal; } - env->stvec = val_to_write >> 2 << 2; break; case CSR_SCOUNTEREN: if (env->priv_ver >= PRIV_VERSION_1_10_0) { @@ -313,11 +314,12 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, env->mepc = val_to_write; break; case CSR_MTVEC: - if (val_to_write & 1) { + /* bits [1:0] indicate mode; 0 = direct, 1 = vectored, 2 >= reserved */ + if ((val_to_write & 3) == 0) { + env->mtvec = val_to_write >> 2 << 2; + } else { qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: vectored traps not supported"); - goto do_illegal; } - env->mtvec = val_to_write >> 2 << 2; break; case CSR_MCOUNTEREN: if (env->priv_ver >= PRIV_VERSION_1_10_0) { |