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authorWeiwei Li <liweiwei@iscas.ac.cn>2023-02-15 10:05:26 +0800
committerPalmer Dabbelt <palmer@rivosinc.com>2023-03-01 14:57:15 -0800
commit1d2cb5a8689f6c087b297723179676132d1cab32 (patch)
treedf862a628813c3abe6e54e951c179d33ac600fa0
parent627634031092e1514f363fd8659a579398de0f0e (diff)
downloadfocaccia-qemu-1d2cb5a8689f6c087b297723179676132d1cab32.tar.gz
focaccia-qemu-1d2cb5a8689f6c087b297723179676132d1cab32.zip
target/riscv: Fix the relationship between Zfhmin and Zfh
Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-2-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
-rw-r--r--target/riscv/cpu.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 93b52b826c..a717f5d995 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -729,7 +729,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
         return;
     }
 
-    if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
+    if (cpu->cfg.ext_zfh) {
+        cpu->cfg.ext_zfhmin = true;
+    }
+
+    if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
         error_setg(errp, "Zfh/Zfhmin extensions require F extension");
         return;
     }