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| author | Pierrick Bouvier <pierrick.bouvier@linaro.org> | 2025-09-22 10:36:53 +0100 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2025-09-26 09:55:19 +0100 |
| commit | 2131f0dcdf97935b1c412e61da51f2de323bfa9c (patch) | |
| tree | ea01d3ddc987b984306482ed5c2df6b0d06a9e7f | |
| parent | a92e151bd0d8c0dedbfb2d301eb31aaac94a1fb8 (diff) | |
| download | focaccia-qemu-2131f0dcdf97935b1c412e61da51f2de323bfa9c.tar.gz focaccia-qemu-2131f0dcdf97935b1c412e61da51f2de323bfa9c.zip | |
target/riscv/common-semi-target: remove sizeof(target_ulong)
Only riscv64 extends SYS_EXIT, similar to aarch64. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250822150058.18692-6-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250922093711.2768983-9-alex.bennee@linaro.org>
| -rw-r--r-- | target/riscv/common-semi-target.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/riscv/common-semi-target.h b/target/riscv/common-semi-target.h index ba40e794dc..7e6ea8da02 100644 --- a/target/riscv/common-semi-target.h +++ b/target/riscv/common-semi-target.h @@ -25,14 +25,14 @@ static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) env->gpr[xA0] = ret; } -static inline bool common_semi_sys_exit_is_extended(CPUState *cs) +static inline bool is_64bit_semihosting(CPUArchState *env) { - return sizeof(target_ulong) == 8; + return riscv_cpu_mxl(env) != MXL_RV32; } -static inline bool is_64bit_semihosting(CPUArchState *env) +static inline bool common_semi_sys_exit_is_extended(CPUState *cs) { - return riscv_cpu_mxl(env) != MXL_RV32; + return is_64bit_semihosting(cpu_env(cs)); } static inline target_ulong common_semi_stack_bottom(CPUState *cs) |