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| author | Richard Henderson <richard.henderson@linaro.org> | 2025-02-04 18:51:30 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2025-02-18 07:33:42 -0800 |
| commit | 252394c95baddf3d61f95cdd0c4697298de425d4 (patch) | |
| tree | bada6d700413d3b0e1bce31237be72649441db61 | |
| parent | 09ac62682b8d2a8bac36d068f63a31331cc6259a (diff) | |
| download | focaccia-qemu-252394c95baddf3d61f95cdd0c4697298de425d4.tar.gz focaccia-qemu-252394c95baddf3d61f95cdd0c4697298de425d4.zip | |
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
The declarations use vaddr for size. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | accel/tcg/cputlb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 17e2251695..75d075d044 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1193,7 +1193,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, hwaddr paddr, MemTxAttrs attrs, int prot, - int mmu_idx, uint64_t size) + int mmu_idx, vaddr size) { CPUTLBEntryFull full = { .phys_addr = paddr, @@ -1208,7 +1208,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr, void tlb_set_page(CPUState *cpu, vaddr addr, hwaddr paddr, int prot, - int mmu_idx, uint64_t size) + int mmu_idx, vaddr size) { tlb_set_page_with_attrs(cpu, addr, paddr, MEMTXATTRS_UNSPECIFIED, prot, mmu_idx, size); |