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| author | Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> | 2018-06-01 11:38:09 -0400 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-06-22 15:01:15 -0300 |
| commit | 254790a909a2f153d689bfa7d8e8f0386cda870d (patch) | |
| tree | dba51d064437242bd185fe98fb8b0b16bbc24bae | |
| parent | a764f3f7197f4d7ad8fe8424269933de912224cb (diff) | |
| download | focaccia-qemu-254790a909a2f153d689bfa7d8e8f0386cda870d.tar.gz focaccia-qemu-254790a909a2f153d689bfa7d8e8f0386cda870d.zip | |
i386: Define AMD's no SSB mitigation needed.
AMD future CPUs expose a mechanism to tell the guest that the
Speculative Store Bypass Disable is not needed and that the
CPU is all good.
This is exposed via the CPUID 8000_0008.EBX[26] bit.
See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf
A copy of this document is available at
https://bugzilla.kernel.org/show_bug.cgi?id=199889
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Message-Id: <20180601153809.15259-3-konrad.wilk@oracle.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7234bebfcb..7a4484bb06 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1009,7 +1009,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "ibpb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - "amd-ssbd", "virt-ssbd", NULL, NULL, + "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, NULL, NULL, NULL, NULL, }, .cpuid_eax = 0x80000008, |